Computer systems often contain multiple processors and a shared main memory. In addition, several cache memories (typically one cache per processor) are often employed to reduce the latency when a processor accesses the main memory. The multiple caches typically share a common bus to the main memory. Each cache memory stores data that is accessed from the main memory so that future requests for the same data can be provided to the processor faster. Each entry in a cache has a data value from the main memory and a tag specifying the address in main memory where the data value came from.
A given data value from the main memory may be stored in more than one cache, and one of the cached copies may be modified by a processor with respect to the value stored in the main memory. Thus, cache coherence protocols are often employed to manage such potential memory conflicts and to maintain consistency between the multiple caches and the main memory. For a more detailed discussion of cache coherency, see, for example, Jim Handy, The Cache Memory Book (Academic Press, Inc., 1998).
The Modified, Exclusive, Shared and Invalid (MESI) protocol is a popular cache coherence protocol that refers to the four possible states that a cache line can have under the protocol, namely, Modified, Exclusive, Shared and Invalid states. A Modified state indicates that the copy is present only in the current cache, and the cache line is dirty (i.e., the copy has been modified relative to the value in main memory). An Exclusive state indicates that the copy is the only copy other than the main memory, and the copy is clean (i.e., the copy matches the value in main memory). A Shared state indicates that the copy may also be stored in other caches. An Invalid state indicates that the copy is invalid.
Cache coherence protocols often involve bus snooping. Generally, bus snooping requires each cache controller to monitor the common bus to detect an access to a memory address that might cause a cache coherency problem. Snoop requests are messages passed among the caches to determine if the caches have a copy of a desired main memory address. The snoop requests may be transmitted by the bus controller to all of the caches in response to read or write requests. Each cache responds to the snoop request with snoop responses. While bus snooping enables cache coherence, bus snooping also consumes resources, such as power and time, and thereby reduces processor efficiency. Thus, cache coherence schemes create an overhead on memory read/write operations, including communications among the caches to maintain and update the coherence state. These communications can degrade overall system performance and increase the latency of the memory read/write operations.
A need therefore exists for improved cache coherence techniques that demonstrate reduced latency relative to conventional techniques.